1. Field of the Invention
This invention relates to semiconductor substrates used chiefly as base members of integrated circuits making use of MOSFETs or bipolar transistors, and a process for their production.
2. Related Background Art
With respect to of silicon type semiconductor devices and integrated circuits, silicon-on-insulator (SOI) structure has been studied at length as a technique which brings about high-speed operation, low power consumption, high integration and total-cost reduction of transistors by making their parasitic capacitance lower and facilitating device isolation.
In the 1970's, Imai proposed FIPOS (full isolation by porous silicon), a process in which the phenomenon of porous-silicon accelerated oxidation is utilized to form the SOI structure (K. Imai, Solid-state Electronics 24, 1981, p.159). In this process, an n-type island is formed on a p-type substrate. Thereafter, the p-type region, inclusive of the part underlying the n-type island, is selectively made porous by anodizing. Meanwhile, the n-type region remains non-porous.
Porous silicon was discovered in 1964 by Uhlir et al. (A. Uhlir, Bell Syst. Tech. J., 35, 1956, p.333), and has, like a sponge, pores of a few nanometers to tens of nanometers in diameter inside the silicon crystal and a surface areas per unit volume of as large as hundreds of m.sup.2 /cm.sup.3 or more. Hence, upon thermal oxidation in an atmosphere containing oxygen, not only the surface of porous silicon but also its interior are simultaneously oxidized by the action of the oxygen having reached the interior of porous silicon, and hence porous layers can selectively be oxidized. The controlling of oxide film thickness relies on the thickness of a porous layer rather than the time of oxidation, and hence it is possible to form a silicon oxide film which is tens to hundreds of times as thick as that formed by oxidation of bulk silicon. That is, the porous region formed can completely be oxidized, and also the silicon island region can be maintained without oxidizing the n-type silicon island completely. This formation of a silicon island on porous silicon by this process is the FIPOS.
Silicon expands in volume upon oxidation. Hence, also in FIPOS, it has been considered preferable for the porous silicon to have a porosity of about 56% [porosity: pore volume/(residual silicon volume+pore volume)] in order to prevent volume expansion due to oxidation and also prevent wafer warpage and concomitant defect inclusion.
As an improvement of this process, a process has been proposed in which porous silicon is formed on the whole surface, thereafter non-porous single-crystal silicon is epitaxially grown on the porous silicon, thereafter part of the epitaxial silicon layer formed is removed to uncover the porous silicon and thereafter the porous silicon is selectively oxidized by thermal oxidation to accomplish the SOI structure (H. Takai and T. Itoh, Journal of Electric Materials 12, 1983, p.973).
As SOI-forming techniques which attract notice recently, an oxygen implantation process (SIMOX, separation by implanted oxygen) and a wafer bonding technology are available.
SIMOX is a process proposed by Izumi et al. in 1978 (K. Izumi, M. Doken and H. Ariyoshi, Electron Letters 14, 1978, p.593) and is a process in which oxygen is implanted in a silicon substrate, followed by heating at a temperature higher than 1,300.degree. C. to form a buried silicon oxide layer. The buried silicon oxide layer has many restrictions because it relies on controlling the defect (or fault) density and oxide film quality.
Meanwhile, with regard to the use of a wafer bonding technique to accomplish the SOI structure, various methods have been proposed since the surface silicon layer and buried silicon oxide layer of the SOI structure can be made to have any desired layer thickness, and the surface silicon layer has a good crystallizability. A direct bonding process in which wafers are bonded to each other without interposing any intermediate layer such as an adhesive layer was proposed by Nakamura et al., but it is after J. B. Lasky et al.'s report in 1984 that this process has begun to be energetically studied; the report (J. B. Lasky, S. R. Stiffler, F. R. White and J. R. Abernathey, Technical Digest of the International Electron Devices Meeting, IEEE, New York, 1985, p.684) was made on a method of forming one of the bonded wafers into a thin film and how MOS transistors formed thereon operate.
As for the bonding technique, epock-making processes have been proposed, as disclosed in Japanese Patent Application Laid-Open No. 5-21338 and U.S. Pat. No. 5,371,037. An example of such a process is as described below: The surface of a single-crystal silicon wafer which is to serve as a first substrate is made porous by anodizing and thereafter a non-porous single-crystal silicon layer is epitaxially grown thereon to provide the first substrate. Thereafter, this is bonded to a second substrate, followed by heating to improve their bond strength, and then the first substrate is removed by grinding or polishing the back thereof to uncover the porous silicon layer over the whole surface. Thereafter, the porous silicon is selectively removed by etching, so that the non-porous single-crystal silicon layer is transferred onto the second substrate. It has become apparent that, as a result of the achievement of selectivity as high as 100,000 times, the uniformity of thickness of the resulting SOI layer is minimally damaged by etching and the uniformity at the time of the growth of the single-crystal silicon layer epitaxially grown is reflected as it is. More specifically, as an in-wafer uniformity achieved by a commercially available CVD epitaxial growth system, a uniformity of from 1.5% to 3% is achieved also in an SOI silicon layer.
In this process, the porous silicon having been used as a material for selective oxidation in FIPOS is used as a material for etching. Accordingly, those having a porosity of about 20% rather than about 56% are preferred. Also, since the porous silicon does not serve as a structural material of the final product, any structural change or coarsening of porous silicon is tolerable so long as the selectivity of etching is not damaged.
A process similar to the above process for producing the SOI structure as disclosed in Japanese Patent Application Laid-Open No. 5-21338 is disclosed also in Yonehara et al.'s report (T. Yonehara, K. Sakaguchi and N. Sato, Appl. Phys. Lett. 64, 1994, p.2108) and is called ELTRAN. In this process, the epitaxial growth of non-porous single-crystal silicon on porous silicon is one of the important techniques, and the stacking fault density in the epitaxial silicon layer on the porous silicon is 10.sup.3 /cm.sup.2 to 10.sup.4 /cm.sup.2, as so reported. In the SOI wafer thus obtained, such stacking faults are the main defects.
Sato et al. (N. Sato, K. Sakaguchi, K. Yamagata, Y. Fujiyama and T. Yonehara, Proc. of the Seventh Int. Symp. on Silicon Mater. Sci. and Tech., Semiconductor Silicon, Pennington, The Electrochem. Soc. Inc., 1994, p.443) have carried out a CVD (chemical vapor deposition) process in which SiH.sub.2 Cl.sub.2 is used as a material gas for the epitaxial growth on porous silicon. Process temperatures are 1,040.degree. C. for prebaking and 900 to 950.degree. C. for the growth; these temperatures which are higher than those in the report on the conventional FIPOS process. However, because of the introduction of preoxidation (400.degree. C. for 1 hour in O.sub.2) for oxidizing pore wall surfaces of porous silicon, structural coarsening of the porous silicon layer is substantially prevented. They report that the defects included in the epitaxial layer are predominantly occupied by the stacking faults and show that reducing the stacking faults contributes to reducing the number of pores of a porous silicon surface by four figures or more, e.g., bringing a density of 10.sup.11 /cm.sup.2 to a low density of 10.sup.7 /cm.sup.2 or less by hydrogen prebaking carried out before the growth in an epitaxial growth furnace. Lowering oxygen concentration in the vicinity of the porous layer surface by hydrofluoric-acid dipping (hereinafter often "HF-acid dipping") carried out immediately before the substrate is set in the epitaxial growth furnace is also effective for lessening the stacking faults. The stacking fault density in the epitaxial silicon layer on porous silicon is lowered to 10.sup.3 /cm.sup.2 or 10.sup.4 /cm.sup.2 by carrying out the HF-acid dipping for a long time, but the lowering of fault density was being saturated. Meanwhile, they suggest that the pores still remaining on the porous silicon surface also after the hydrogen prebaking are the origin of stacking faults. Growth rate is substantially above 100 nm/minute.
Sato et al. (N. Sato et al., Jpn. J. Appl. Phs. 35, 1996, p.973) also disclose that, in the epitaxial growth on porous silicon, the feeding of material silicon in a very small rate at the initial growth stage enables surface diffusion of silicon atoms adsorbed on the surface and makes it hard for crystal defects to be included even in residual pores, thereby lowering the crystal defect density. A similar technique is also disclosed in Japanese Patent Application Laid-Open No. 9-100197 and EP 755068.
Without limitation to the SOI structure, the non-porous single-crystal layers formed on porous silicon layers by conventional processes are sought to be improved in terms of smoothness of their surfaces and the porous silicon layers are also sought to be improved in terms of smoothness of the surface where the surface pores have been sealed up.